Machine Learning Theory and Practice, 2026, 6(1); doi: 10.38007/ML.2026.060106.
Enqi Weng
School of Economics, Wuhan Donghu University, Wuhan, 430000, Hubei, P.R. China
To address the challenges in option pricing caused by the large sample size, latency sensitivity, and power consumption limitations of Monte Carlo simulations, this paper conducts in-depth research on four aspects: algorithms, random numbers, parallel pipelining, and resource mapping, and proposes a hardware acceleration engine framework based on FPGA. After reviewing the research progress of FPGAs in option pricing, quantitative finance, and random number generation over the past three years, the paper proposes an architecture goal for low-latency scenarios. This architecture focuses on three main aspects: geometric Brownian motion path generation, discounted return accumulation, and statistical error control, implemented using streaming data paths, path-level parallelism, on-chip random number supply, and fixed-point/floating-point co-design. The paper then presents the pricing model, discretization formula, throughput and energy efficiency evaluation indicators, and discusses the implementation methods from four aspects: module partitioning, pipelining scheduling, memory access organization, and precision control. By redrawing statistical graphs using the latest publicly available research data and conducting comparative analysis, it is shown that Versal-type AIE/PL co-design has significant advantages in throughput and energy consumption during large-scale path simulations. However, its performance ultimately depends on factors such as on-chip interconnects, random number generation bandwidth, and host-device coupling methods. Research findings indicate that the key to using FPGAs for Monte Carlo simulation of option prices lies not in parallelism, but in integrating random number generation, path movement, payout accumulation, and error control into a single pipeline using a reusable hardware engine.
FPGA; option pricing; Monte Carlo simulation; hardware acceleration; low-latency computing
Enqi Weng. Research on Monte Carlo Simulation Implementation of Option Pricing Based on FPGA Hardware Acceleration Engine for Low-Latency Derivatives Computation. Machine Learning Theory and Practice (2026), Vol. 6, Issue 1: 49-58. https://doi.org/10.38007/ML.2026.060106.
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